Serial in Serial out Shift Register Watch more videos at Lecture By: Ms. Gowthami Swarna, Tutorials Point India Private Limited.
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Just to be fair, this is a previous exam question and was an assignment question. I've already handed in the assignment and now I'm trying to see why I got it wrong -- to study for my final.
I fully understand how to find the 2's complement of a binary number, however, implementing a circuit to find the complement is driving me crazy. I'm given a shift register (that stores my binary number) and a flip flop (using D for simplicity). The process I follow for building sequential circuits is this:
- I look at the question and derive a state diagram.
- From the state diagram, I draw a state table and find the input of my flip flops
- I use maps and stuff to finally build the circuit.
I'm trying to visualize how to actually draw the state diagram for this complementer. I know it depends on the previous value and stuff, but if someone could take the time to explain in plain english how he/she would go about building the state diagram, I would be vey grateful.
3 Answers
$begingroup$That link you gave says it all:
Hint: - 2’s complement of a number can be obtained by keeping the least significant bits as such until the first 1, and then complementing all bits
'example 001010 → 110110' that is to say
So there are two states - 'I haven't seen a one yet' and 'I have seen a one previously'. Given my state and my current input, my output and next state are fully determined.
If my current state is 'I haven't seen a one yet' and my input is a 0, my output is a 0 and my next state is (still) 'I haven't seen a one yet'
If my current state is 'I haven't seen a one yet' and my input is a 1, my output is a 1 and my next state is (changes to) 'I have seen a one previously'
If my current state is 'I have seen a one previously' and my input is a 0, my output is a 1 and my next state is (still) 'I have seen a one previously'
If my current state is 'I have seen a one previously' and my input is a 1, my output is a 0 and my next state is (still) 'I have seen a one previously'
Write that out as a truth table encoding 'I haven't seen a one yet' as 0 and 'I have seen a one previously' as 1, and you should be home free.
To 'wire it up' the current data input bit and the current state go into logic that feeds the input to the D-flip flop and separate logic that feeds the input to the shift register, the D-flip-flop holds the 'state variable', and both are clocked by the data clock. And to be complete you need some kind of reset logic - left as an exercise to the reader. The 'current state' is the output of the D-flip-flop, and next state is the input to it...
vicatcuvicatcuYou know the 2's complement of each of the binary values 0000, 0001, 0010, 0011, ... 1111, right?
There are at least 2 ways to get the 2's complement of a number in a SIPO shift register:
direct combinatorial logic. Take the 4 bits of the value, (simultaneously) invert all the bits and (simultaneously) add one. (I think a bunch of half-adder circuits are adequate here -- you can copy those out of your textbook, right?) There is no flip-flop or other internal state with this approach.
Serial incrementer. Starting with the least-significant bit, shift one bit at a time into a serial incrementer (a single half-adder and a single D flip flop). The serial incrementer generates (one bit at a time), from the current bit from the shift register and a Carry_in bit, the Carry_out bit and the Sum bit. Every clock cycle, the old Carry_out bit is latched into your D flip flop and becomes the new Carry_in bit, and the next bit comes out of the shift register. Then the half-adder combinational logic combines them to produce another Carry_out bit and Sum bit. (The flip-flop also needs some way to reset the carry bit it holds to '1' when starting over with the least-significant bit of a new number).
When adding 2 bits, the Carry_out is 1 only when both bits are 1; otherwise the Carry_out is zero.
davidcarydavidcarystate diagram is just the output to next
for a mod 3 count up counter the state diagram would be
000 -> 001 -> 010 -> back to 000
since it counts from 0 to 2 and reset on 3
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My question:
State table:
i started by forming 2 states(S0 and S1) since we have only 1 flopflop.At S0 when input=0 hold (output will be equal to 0) otherwise move to the next state(S1),I dont know exactly why the output=1 in this case .Finally,At S1 when input=0 then output=1 and when input =1 then output =0.
I'd like to have an explanation of this problem. My final exam is tomorrow.
1 Answer
$begingroup$First look at the operation of the D type flip flop
The sequence starts by a reset so Q = 0
The input to the D-type is made up from the initial output (Q) which is OR'd with the first (LSB) bit of the number you are complimenting (X).
The output Y is XOR'd with Q and X (00 > 0, 01 >1) as Q is '0' we don't have to consider any other case. So initially the output at Y will always be the same as input at X i.e our LSB data bit.
The initial input at 'D' will also be the same as the input at X (X OR '0' = X)
Let's take a number - say 28. In binary this would be 00011100To change this to its 2's compliment we invert and add 1
So if our circuit works a 00011100 input it will produce a 11100100 output
Start with a reset so that Y = X (Q = '0')
Serial 2 S Complementer Shift Register Of Deeds
LSB first
Serial 2 S Complementer Shift Register Online
Look at the diagonal relationship between D and Q. Q in the next row (t+1) is simply the value of D in the previous row (at time t). Each time the bit is CLOCKED 't' moves on 1. The rest is simply applying the logic of the connected gates to produce a value.